Welcome to the Quantitative Analysis Group!
The Quantitative Analysis Group is committed to evaluating the performance of computer devices through data metrics, thus proposing optimization decisions at hardware level.
We employ methodologies, including benchmarking, simulation, modeling, etc., to assess and explore hardware designs at the micro-architectural level, particularly processors and memory.
If you are interested in learning and working on Quantitative Analysis or Computer Architecture, please consider joining our group.

Projects

We are currently collaborating with OPPO, and have established the SEU-OPPO Joint R&D Center for Software and Hardware Co-innovation of Intelligent Terminal System. There are 2 projects running in the Joint R&D Center, and more projects is coming soon.

Benchmark Program Synthesis

During the early stages of processor design, simulators are widly used for prototype validation. However, this method faces 2 significant challenges. First, the large number of dynamic instructions in benchmark programs leads to prolonged simulation times. Second, existing open-source or commercial benchmark programs often fail to fully meet the requirements of prototype verification.
To solve these problems, the research team is developing methods for benchmark programs synthesis. Based on the characteristics of the application programs, our goal is to synthesize benchmark programs with similar performance metrics but significantly reduced numbers of dynamic instructions. In the end, the new testbench can shorten simulation time and better fulfill the requirements of prototype verification.

Data Access Normalization on the CPU to Multi-Level Cache and DDR SDRAM

This project focus on the development of a simulation platform for memory subsystem analysis. In this platform, we can meticulous adjust various cache levels (L1/L2/L3/SLC) and DDR parameters, and acquire essential execution data. With this data, users can accurately determine the most energy-efficient design strategies for the memory subsystem.

Publications

A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools

• Ming Ling, Hongxi Li, Xiang Yu
• 2022 IEEE Embedded Systems Letters
• DOI: 10.1109/LES.2021.3113347

Collaborating Company

Last edited in 2024.4