Publications
2024
Preventing short violations in clock routing with an SVM classifier before powerplanning and placement
- Qi Liu, Ming Ling, Yanxiang Zhu, Yibo Rui, Rui Wang
- 2024 Microelectronics Journal
- DOI: 10.1016/j.mejo.2024.106429
Modeling Equivariant Neural Networks for Hardware Acceleration, a Case Study on the Molecular Docking Tool DiffDock
- Shidi Tang, Xingxing Zhou, Ming Ling
- 2024 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)
- DOI: 10.1109/PACRIM61180.2024.10690224
Ultra8T: A sub-threshold 8t sram with leakage detection
- Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu
- 2024 Integration
- DOI: 10.1016/j.vlsi.2024.102233
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool with High-Accuracy and Multi-Level Parallelism
- Ming Ling, Zhihao Feng, Ruiqi Chen, Yi Shao, Shidi Tang, Yanxiang Zhu
- 2024 IEEE Transactions on Biomedical Circuits and Systems (TBCAS)
- DOI: 10.1109/TBCAS.2024.3388323
2023
Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool Autodock Vina
- Xingxing Zhou, Ming Ling, Qingde Lin, Shidi Tang, Jiansheng Wu, Haifeng Hu
- 2023 IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
- DOI: 10.1109/TCBB.2023.3323552
Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units
- Ji Ding, Shidi Tang, Zheming Mei, Lingyue Wang, Qinqin Huang, Haifeng Hu, Ming Ling, and Jiansheng Wu
- 2023 Journal of Chemical Information and Modeling (JCIM)
- DOI: 10.1021/acs.jcim.2c01504
A Novel Delay Calibration Method Considering Interaction between Cells and Wires
- Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi
- 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
- DOI: 10.23919/DATE56975.2023.10136932
2022
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism
- Ming Ling, Qingde Lin, Ruiqi Chen, Haimeng Qi, Mengru Lin, Yanxiang Zhu, Jiansheng Wu
- 2023 IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
- DOI: 10.1109/TVLSI.2022.3217275
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model
- Shan Shen, Peng Cao, Ming Ling, Longxing Shi
- 2023 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
- DOI: 10.1109/TCAD.2022.3194812
Accelerating autodock vina with gpus
- Shidi Tang, Ruiqi Chen, Mengru Lin, Qingde Lin, Yanxiang Zhu, Ji Ding, Haifeng Hu, Ming Ling, Jiansheng Wu
- 2022 Molecules
- DOI: 10.3390/molecules27093041
2021
Mlof: Machine learning accelerators for the low-cost fpga platforms
- Ruiqi Chen, Tianyu Wu, Yuchen Zheng, Ming Ling
- 2021 Applied sciences
- DOI: 10.3390/app12010089
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages
- Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang
- 2021 IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
- DOI: 10.1109/TVLSI.2021.3120653
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools
- Ming Ling, Hongxi Li, Xiang Yu
- 2022 IEEE Embedded Systems Letters
- DOI: 10.1109/LES.2021.3113347
A fast cross-layer dynamic power estimation method by tracking cycle-accurate activity factors with spark streaming
- Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi
- 2021 IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
- DOI: 10.1109/TVLSI.2021.3111000
Analytical modeling the multi-core shared cache behavior with considerations of data-sharing and coherence
- Ming Ling, Xiaoqian Lu, Guangmin Wang, Jiancong Ge
- 2021 IEEE Access
- DOI: 10.1109/ACCESS.2021.3053350
2020
VASTA: A wide voltage statistical timing analysis tool based on variation-aware cell delay models
- Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi
- 2020 IEEE Access
- DOI: 10.1109/ACCESS.2020.3035263
Fast modeling L2 cache reuse distance histograms using combined locality information from software traces
- Ming Ling, Jiancong Ge, Guangmin Wang
- 2020 Journal of Systems Architecture
- DOI: 10.1016/j.sysarc.2020.101745
TYMER: A yield-based performance model for timing-speculation SRAM
- Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi
- 2020 ACM/IEEE Design Automation Conference (DAC)
- DOI: 10.1109/DAC18072.2020.9218623
A cross-layer power and timing evaluation method for wide voltage scaling
- Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi
- 2020 ACM/IEEE Design Automation Conference (DAC)
- DOI: 10.1109/DAC18072.2020.9218682
Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM
- Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi
- 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
- DOI: 10.23919/DATE48585.2020.9116569
Publications since 2020 are listed
Last edited in 2024.10